DOI : https://doi.org/10.62527/ijasce.3.1.34

FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder

Saba Azeez (1), Pankaj Rangaree (2)
(1) E & C Department, Vaagdevi College of Engineering, Warangal, India
(2) E & C Department, Vaagdevi College of Engineering, Warangal, India
Fulltext View | Download
How to cite (IJASEIT) :
Azeez, S., & Rangaree, P. (2021). FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder. International Journal of Advanced Science Computing and Engineering, 3(1), 10–17. https://doi.org/10.62527/ijasce.3.1.34
Citation Format :
Three operand binary adder is the basic functional unit to perform the pseudorandom bit generator algorithms and in various cryptography. The basic method used to perform the three-operand binary addition is carry save adder, which leads to high delay. For this a parallel prefix two operand adder such as Han-Carlson adder is used to reduce the delay but increases the hardware architecture i.e., area increases. To overcome this disadvantage, we need a new area efficient and high-speed adder architecture to be proposed using pre compute bitwise addition followed by carry prefix computation logic to perform three operand binary adder which reduces delay and area efficiently. This method is the proposed method and implemented on the FPGA device. A newly designed three operand binary adder is shown and is implemented in MDCLCG. The results of 16 bit and 32-bit three operand adder will be shown and this proposed method is applied on Modified Dual CLCG. The Carry-Save-Adder architecture used in 32-bit MDCLCG is replaced by the proposed architecture. The design is prototyped on a commercially available FPGA platform to validate the design on silicon chip.

M. M. Islam, M. S. Hossain, M. K. Hasan, M. Shahjalal, and Y. M. Jang, “FPGA implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field,†IEEE Access, vol. 7, pp. 178811–178826, 2019.

A. Kumar Panda and K. Chandra Ray, “A coupled variable input LCG method and its VLSI architecture for pseudorandom bit generation,†IEEE Trans. Instrum. Meas., vol. 69, no. 4, pp. 1011–1019, Apr. 2020.

A. K. Panda and K. C. Ray, “Modified dual-CLCG method and its VLSI architecture for pseudorandom bit generation,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 3, pp. 989–1002, Mar. 2019.

K. S. Pandey, D. K. B. N. Goel, and H. Shrimali, “An ultra-fast parallel prefix adder,†in Proc. IEEE 26th Symp. Comput. Arithmetic (ARITH), Kyoto, Japan, Jun. 2019, pp. 125–134.

F. Jafarzadehpour, A. S. Molahosseini, A. A. Emrani Zarandi, and L. Sousa, “New energy-efficient hybrid wide-operand adder architecture,†IET Circuits, Devices Syst., vol. 13, no. 8, pp. 1221–1231, Nov. 2019.

Z. Liu, J. GroBschadl, Z. Hu, K. Jarvinen, H. Wang, and I. Verbauwhede, “Elliptic curve cryptography with efficiently computable endomorphisms and its hardware implementations for the Internet of Things,†IEEE Trans. Comput., vol. 66, no. 5, pp. 773–785, May 2017.

Z. Liu, D. Liu, and X. Zou, “An efficient and flexible hardware implementation of the dual-field elliptic curve cryptographic processor,†IEEE Trans. Ind. Electron., vol. 64, no. 3, pp. 2353–2362, Mar. 2017.

S.-R. Kuang, K.-Y. Wu, and R.-Y. Lu, “Low-cost high-performance VLSI architecture for Montgomery modular multiplication,†IEEE Trans. Very Large Scale Integer. (VLSI) Syst., vol. 24, no. 2, pp. 434–443, Feb. 2016.

S. S. Erdem, T. Yanik, and A. Celebi, “A general digit-serial architecture for Montgomery modular multiplication,†IEEE Trans. Very Large-Scale Integer. (VLSI) Syst., vol. 25, no. 5, pp. 1658–1668, May 2017.

A. Rezai and P. Keshavarzi, “High-throughput modular multiplication and exponentiation algorithms using multibit-scan–multibit-shift technique,†IEEE Trans. Very Large-Scale Integer. (VLSI) Syst., vol. 23, no. 9, pp. 1710–1719, Sep. 2015.