AZEEZ, Saba; RANGAREE, Pankaj. FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder. International Journal of Advanced Science Computing and Engineering, [S. l.], v. 3, n. 1, p. 10–17, 2021. DOI: 10.62527/ijasce.3.1.34. Disponível em: https://ijasce.org/index.php/IJASCE/article/view/34. Acesso em: 6 may. 2024.