Azeez S, Rangaree P. FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder. Int. J. of Adv. Sci. Comp. and Eng. [Internet]. 2021 Jun. 28 [cited 2024 Nov. 23];3(1):10-7. Available from: https://ijasce.org/index.php/IJASCE/article/view/34